March 23, 2008 Since I'm such a meddler, as drilled in codes like BIOS, and he will not rest until the screen for good nezčerná :), and also need to be able to manually reprogram FlashROM. I used it in parallel flashek that were on the board at DIL32 or PLCC32 socket, solved simply hotflash when I had prepared in advance of the second chip with a working BIOS. The one I put into the slot at runtime exchange for badly programmed chip and reprogrammed.
Now I'm on my new motherboard
Gigabyte GA-P31-DS3L met with a new type of memory - a high speed SPI FlashROM
Winbond 25X40VSIG SMD SOIC-8 housing, which is soldered directly to the board. South bridge intel ICHx longer time support both variants FWH and SPI. Using certain chipset registers and pins can select from the interface is primarily used for BIOS.
Due to the fact that with SMD components save a dime at base, overall reducing the costs of production and thus managers have more $ for better cars and bitches ;). Šťouralům then we have no choice but to take the hand solder ... To flash with that reasonably could work, I soldered it to the precise DIL8 slot. The second slot DIL8 I then soldered to the motherboard. Because I would be on-site with a solder around the base (opposite the SATA connector) did not make it, I let it dangle on two bits of 4-core braces:
Followed by a production programmer. SPI devices to connect to the PC but just an ordinary parallel port, 5 wire, a few resistors and connectors. Involvement based on the type of cable programming SPI BSD programming Atmel AVR microcontrollers. Advertised W25X40V memory is designed for 3.3 V power supply, so I separated the data line resistors, to suffer from a higher voltage LPT. At the same time acts as a damping resistors, otherwise it will on the long (about 1.5 meters) flat cable without shielding between the signal lines causing crosstalk and thus incorrect data transmission. Interestingly, the same AVR MCU me a lead they work without problems. I used to power an external source.
The whole thing then jumbled the universal plošňáku looks something like this:
Another thing that is only software that I had to write. First, it must be programmed lowest layer that works with LPT registers and sets / reads the required level of the SPI lines. On this topic, I refer to the book Burkhard Kainka - Using the PC port of Publishing HEL 1997, from which I once learned how to blink his first light on LPT. But the Internet is a resource on this topic more than enough.
In addition, I said something to the SPI bus itself. It consists of three lines: SCK - Serial Clock (up to tens of MHz), MISO - Master Output Slave Input, MOSI - Master Output Slave Input and in this case there is also an auxiliary control unit # CS - Chip Select. Communication typically takes place between two devices, one of which is the master (in this case the PC), which controls the SCK clock (there is a resting level log. 0) and sends commands / data on MOSI line while simultaneously reads the data from the MISO line.
Slave devices (in this case, memory) then responds to the SCK clock by the falling edge of the clock sends a bit on the MISO line and the rising edge of the bit clock reads MOSI lines. Byte is sent in MSB first, LSB last. After the transfer is complete master clock returns to the idle level (logical 0). The bus is to be opposed by I2C full duplex. Slave devices do not identify any address. In order to connect to multiple lines SPI slave devices must be master with any device connected to a separate control line CS # to log levels. N 0, activates one slave device (other SPI outputs are in high impedance state to affect the ongoing communication (SPI devices have 3-state outputs are required pull-ups). In the case of SPI Flash memory, CS # is used for the beginning and end of the frame so it can not be easily connected to the ground. following picture tells more as being read from memory:
First Master starts moving beyond CS # to log. 0 and thereby activates the memory. Then starts the master clock and transmits the first byte command 3h - reading from memory. Memory determines, what we want to her and knows he has yet to address. Then the master sends the next 3 bytes. Memory address decoding and immediately starts the next byte to send data. If Master requests data from the following addresses, lets start the clock and automatically increments the memory address. Further incoming data from the Master are ignored. End of the frame, then the Master terminates transfer hours in standby log. 0 and CS # going to idle status log.
First memory supports a standard set of commands, which include the need to read, write, delete pages, erasing sectors, deleting the whole chip, lock, unlock, identifying the manufacturer and type of chip JEDEC, reading the status register, ... Some commands are byte, others have parameters and data. Some memory corresponds sending data to another Sun For more details see datasheet for specific memory.
Further step was therefore write functions for sending and receiving bytes and data blocks, and finally processing functions commands of Flash memory. The current version of the program allows you to identify the type of memory / i, to read and display the data block of a given size from a given address / r, read the entire file into memory / d, the entire program memory from / p, delete the entire memory / ea unlock write protect bits / u . Other parameters / L = Adjustable base address of LPT / d = extension of SCK pulse in microseconds (except Windows version, where there is no timer with a higher resolution than 1 ms). The download package are 3 versions for DOS, Windows and Linux.
Due to the limited speed of LPT and serial transmission method takes a read or write tens of seconds to minutes. Chip erase time depends on the speed of the internal mechanisms in memory and takes about units to tens of seconds. Faster communication could be achieved using microcontroller, preferably with a hardware SPI controller, which communicates with the PC either 8-bit after LPT or USB. Sample event program memory M25P32 Wed: More information at
Rayer's Blog.
